Technology
Subject: COMPUTER ARCHITECTURE (A.A. 2022/2023)
degree course in COMPUTER ENGINEERING
| Course year | 1 |
|---|---|
| CFU | 9 |
| Teaching units |
Unit architettura dei calcolatori
Mathematics, Information Technology and Statistics (lesson)
|
| Moodle portal | |
| Exam type | written |
| Evaluation | final vote |
| Teaching language | Italiano |
Teachers
Overview
The course aims at providing basic knowledge on modern computer architectures. Starting from fundamental logic gates and logic circuits, the students will be guided toward the development of a working processor prototype, so as to better understand its main architectural elements. Specifically, basic knowledge on the RISC-V microarchitecture and the corresponding assembly languages is provided, also by means of practical activities. Key notions about the memory hierarchy and the virtual memory system of a modern computer will also be provided.
Admission requirements
The course does not require any specific prerequisite, but some skills about the imperative programming paradigm are recommended
Course contents
- INFORMATION REPRESENTATION [1 CFU]
Positional notation
Binary and hexadecimal encoding, two's complement
Fixed point and floating point representations. The IEEE 754-1985 standard
- COMBINATIONAL LOGIC CIRCUITS [1 CFU]
Boolean algebra, expressions and theorems
Synthesis of combinational circuits
Karnaugh maps, normal and minimal forms
Decoder, Multiplexer, Half and Full Adder, ALU
- SEQUENTIAL LOGIC CIRCUITS [1 CFU]
SR latch, D latch, SR, D, JK and T Flip-flop
Synthesis of sequential circuits
Finite state machines (Mealy, Moore), state diagrams
Counter, Register, Memory Bank
- AN INTRODUCTION TO THE RISC-V INSTRUCTION SET [2 CFU]
RISC-V registers and operands (register, memory, immediate)
RISC-V instruction formats: R, I, S.
Conditional operations and procedure calling.
Synchronization instructions
Compiling, linking and loading a program.
Effects of compiler optimizations.
- COMPUTER ARITHMETICS [1.5 CFU]
Integer addition and subtraction. Overflow
Multiplier and Divider hardware
RISC-V instructions for multiplication and division
IEEE 754 floating-point support: hardware and RISC-V instructions
Subword parallelism: SIMD extensions
- THE PROCESSOR [1.5 CFU]
CPU overview. Instruction execution.
Building datapath and control HW
Pipelined RISC-V CPU design
Structural, data and control hazards. Forwarding
Branch prediction
Instruction-level parallelism (ILP): out-of-order execution (OoO) and very-long instruction word (VLIW)
- MEMORY SUBSYSTEM [1 CFU]
Locality and memory hierarchies
Introducing the cache. Direct mapped caches
Cache miss. Write-back and write-through
Associative cache. Replacement policies
Multilevel caches. Performance
Virtual memory
Teaching methods
Traditional lectures with slides and blackboard are used for the theoretical part of the course, which are complemented by laboratory exercises. Finally, one or two seminars are organised towards the end of the course.
Assessment methods
The exam is composed of a written test and a (non-mandatory) oral part. The written test consists of exercises with questions having a single correct answer, multiple answers or an open answer. During this examination it is forbidden to use any tipe of teaching material, books or similar. The participation to a written exam invalidates the score obtained in previous exams. After communicating the score of the written exam, the student may decide to register the score (if sufficient), or participate to the oral exam to potentially increase the score. The oral exam can be given only by students that obtained a score of 15 or above in the written exam. The score in the written exam remains valid for one academic year. The oral part covers all the theoretical concepts, and can be replaced by a project, where the students apply in practice what they have learned in the course. These projects are presented at the end of the course. In case the student decides to take the oral exam, the final score will be the average between the written and oral parts.
Learning outcomes
Knowledge and understanding
Binary representation of information
logic circuits
computer architecture
Applying knowledge and understanding
skills using binary representation
boolean logic
Analysis and synthesis of simple logic circuits, both combinational and sequential ones
Assembly programming skills
Making judgements:
Ability to recognize and evaluate computer's features and performance. Ability to find the best solution to a given problem. To this aim, during the written test the student is allowed to use notes and books.
Communication skills
The student should present and revise his knowledge, with a particular focus on the lexicon and technical jargon.
Learning skills:
students will learn a very low-level language, far to their usual abstraction level and intuitive developing schema.
Moreover, they have to delve into collateral aspects of the discussed arguments.
Readings
M. Morris Mano, Charles Kime, Tom Martin, "Reti logiche", 5/Ed., Pearson Editore
ISBN: 9788891905819
https://www.pearson.it/opera/pearson/0-6794-reti_logiche
David A Patterson, John L Hennessy, "Struttura e progetto dei calcolatori - Progettare con RISC-V" Edizione italiana a cura di Alberto Borghese. Zanichelli Ed.
ISBN: 9788808820594
https://www.zanichelli.it/ricerca?q=978.8808.82059.4
Giacomo Bucci, "Calcolatori elettronici. Architettura e organizzazione", Mc. Gray Hill
ISBN: 9788838664700
http://www.catalogo.mcgraw-hill.it/catLibro.asp?item_id=2410
G. Conte, A. Mazzeo, N. Mazzocca, P. Prinetto , "Architettura dei calcolatori", CittàStudiEdizioni. ISBN: 9788825173642
http://www.cittastudi.it/catalogo/scienze/architettura-dei-calcolatori-3540