Subject: COMPUTER ARCHITECTURE (A.A. 2020/2021)
Unit Architettura dei calcolatori
Information Technology (lesson)
The course aims at providing basic knowledge on modern computer architectures. Starting from fundamental logic gates and logic circuits, the students will be guided toward the development of a working processor prototype, so as to better understand its main architectural elements. Specifically, basic knowledge on the RISC-V microarchitecture and the corresponding assembly languages is provided, also by means of practical activities. Key notions about the memory hierarchy and the virtual memory system of a modern computer will also be provided.
The course does not require any specific prerequisite, but some skills about the imperative programming paradigm are recommended
- INFORMATION REPRESENTATION.
Binary and hexadecimal encoding, two's complement
Fixed point and floating point representations. The IEEE 754-1985 standard
- COMBINATIONAL LOGIC CIRCUITS
Boolean algebra, expressions and theorems
Synthesis of combinational circuits
Karnaugh maps, normal and minimal forms
Decoder, Multiplexer, Half and Full Adder, ALU
- SEQUENTIAL LOGIC CIRCUITS
SR latch, D latch, SR, D, JK and T Flip-flop
Synthesis of sequential circuits
Finite state machines (Mealy, Moore), state diagrams
Counter, Register, Memory Bank
- AN INTRODUCTION TO THE RISC-V INSTRUCTION SET
RISC-V registers and operands (register, memory, immediate)
RISC-V instruction formats: R, I, S.
Conditional operations and procedure calling.
Compiling, linking and loading a program.
Effects of compiler optimizations.
- COMPUTER ARITHMETICS
Integer addition and subtraction. Overflow
Multiplier and Divider hardware
RISC-V instructions for multiplication and division
IEEE 754 floating-point support: hardware and RISC-V instructions
Subword parallelism: SIMD extensions
- THE PROCESSOR
CPU overview. Instruction execution.
Building datapath and control HW
Pipelined RISC-V CPU design
Structural, data and control hazards. Forwarding
Instruction-level parallelism (ILP): out-of-order execution (OoO) and very-long instruction word (VLIW)
- MEMORY SUBSYSTEM
Locality and memory hierarchies
Introducing the cache. Direct mapped caches
Cache miss. Write-back and write-through
Associative cache. Replacement policies
Multilevel caches. Performance
Lectures with slides for the theoretical part of the course, complemented by exercises. Remote access to the classes and materials will be provided. Depending on the evolution of the COVID19 pandemic situation traditional taught classes will be delivered.
There are six examination sessions in a year. The examination is composed by a written test and an oral part. The written test, approximately one hour and a half long, consists of questions with a single or multiple correct answers, to assess the knowledge of the theory, plus exercises or questions with an open answer to evaluate the understanding of more practical topics from the course. During this examination it is forbidden to use any tipe of teaching material, books or similar. The oral part covers all the theoretical and practical concepts, and is based on the outcome of the written test (typically a barely sufficient score at the written test requires an in-depth oral examination). The final score is the average of the scores achieved in the written and oral tests. The tests might be conducted remotely or in presence depending of the evolution of the COVID19 pandemic situation.
Knowledge and understanding
Binary representation of information
Applying knowledge and understanding
skills using binary representation
Analysis and synthesis of simple logic circuits, both combinational and sequential ones
Assembly programming skills
Ability to recognize and evaluate computer's features and performance. Ability to find the best solution to a given problem. To this aim, during the written test the student is allowed to use notes and books.
The student should present and revise his knowledge, with a particular focus on the lexicon and technical jargon.
students will learn a very low-level language, far to their usual abstraction level and intuitive developing schema.
Moreover, they have to delve into collateral aspects of the discussed arguments.
Per la parte di reti logiche:
M. Morris Mano, Charles Kime, Tom Martin, "Reti logiche", 5/Ed., Pearson Editore
Per la parte di architettura dei calcolatori, microarchitettura e assembly RISC-V:
David A Patterson, John L Hennessy, "Struttura e progetto dei calcolatori - Progettare con RISC-V" Edizione italiana a cura di Alberto Borghese. Zanichelli Ed.
Più le dispense fornite dal docente.
Giacomo Bucci, "Calcolatori elettronici. Architettura e organizzazione", Mc. Graw Hill